1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and a data erasing method thereof. For example, the invention relates to a NOR type flash memory and an NAN flash memory, in both of which blocks each comprising a plurality of memory cells are provided, and a data erasing processing is performed in units of one block, and also to a data erasing method applied to those flash memories.
2. Description of the Related Art
In a nonvolatile semiconductor memory device, electrons are injected into or eliminated from a number of memory cells (each corresponding to 1-bit data), whereby the threshold values of the memory cells are changed, and the data stored in each memory cell indicates “1” or “0” (in the case where the memory cells store multivalue data, the injected charge can take one of four levels according to the stored data).
In general, in a nonvolatile semiconductor memory device referred to as a NOR type flash memory, in programming (writing) (in which electrons are injected into a memory cell or cells), a memory cell to which data can be written in units of 1 bit can be designated. This is because when a bit line and a word line are designated, and voltages are applied to the bit line and the word line, a bias is set to enable the above memory cell only to be subjected to the programming. However, in an actual nonvolatile semiconductor memory product, a number of bits are written as programming at the same time, i.e., a number of memory cells are subjected to the programming at the same time, in order that the programming be carried out at a higher speed.
On the other hand, in a data erasing operation, a bias is applied to a word line and a well region, and thus memory cells sharing the well region with each other are all erased as a data erasing processing (generally, the data erasing processing is executed in units of one block consisting of a number of memory cells). Thus, the data erasing processing of the nonvolatile semiconductor memory device comprises the following series of operations (steps), which will be explained with reference to FIG. 1, which is a flowchart of a series of step in a data erasing operation in a conventional nonvolatile semiconductor memory device.
First, in a block in which memory cells storing data indicating “1” (which are in an erased state) and memory cells storing data indicating “0” (which are in a programmed (written) state) are randomly present, only the memory cells storing the data indicating “1” are subjected to preprogramming (i.e., writing before the data erasing processing) in which the threshold value of a memory cell or cells to be processed is set to be equal to or higher than a voltage program verify (PV) level (step S101). FIG. 11A shows distribution of the threshold values of the memory cells not yet subjected to the above preprogramming, and FIG. 11B shows distribution of the threshold values of the memory cells subjected to the preprogramming.
Then, all the memory cells in the block are erased as a data erasing processing (step S102). In this processing, the threshold values of the memory cells are all lowered to be equal to or lower than a voltage erase verify (EV) level. FIG. 11C shows distribution of the memory cells subjected to the above data erasing processing.
However, actual memory cells vary in dimensions and thickness, etc. Thus, actually, of the above memory cells subjected to the above data erasing processing, a memory cell or cells are in an over-erased state in which their threshold values are lower than a voltage over erase verify (OEV) level. Therefore, weak programming is performed on a memory cell or cells determined to be in the over-erased state with respect to the voltage OEV level.
The following is the weak programming of the conventional nonvolatile memory device:
First, it is verified as a verifying processing whether or not the threshold value of each of the memory cells is equal to or higher than the voltage OEV level (step S103). When it is verified that the threshold value of a memory cell is lower than the voltage OEV level, i.e., the memory cell is in the over-erased state, it is subjected to the weak programming (step S104). This weak programming does not mean programming (writing) performed by applying a high voltage for making the data stored in the memory cell indicate “0”, i.e., it means programming (writing) performed by applying a voltage lower than the high voltage to the drain and gate in the memory cell.
After being subjected to the weak programming in the above manner, the above memory cell is re-subjected to the verifying processing (step S103). Also, when it is verified that the threshold value of the memory cell is still lower than the voltage OEV level, and the memory cell is re-subjected to the weak programming (step S104). The verifying processing and the weak programming are repeated until it is verified that the threshold value of the memory cell is equal to or higher than the voltage OEV level. Then, when it is verified that the threshold value of the memory cell is equal to or higher than the voltage OEV level, the memory cell to be processed is changed from the above memory cell to a memory cell subsequent thereto (step S105).
After the weak programming on all the memory cells in the over-erased state in the block is completed (step S106), it is verified whether or not the threshold values of all the memory cells exceed the voltage EV level (step S107). Then, when there is no memory cell whose threshold value exceeds the voltage EV level, the data erasing processing ends. On the other hand, when there is a memory cell or cells the threshold values of which exceed the voltage EV level, the step is returned to the step S102 (data erase processing), and the steps are successively carried out from the step S102. Those series of steps are carried out as the steps in the data erasing operation in the conventional semiconductor memory device.
However, the above conventional semiconductor memory device has the following problem:
After the data erasing processing, there is a case where a singular memory cell (which will be hereinafter referred to a singular memory cell B) is present which is subjected to data erasing such that its threshold value is far lower than the voltage OEV level. This problem arises even in the case where the first threshold values of the memory cells are equalized by the preprogramming. It can be considered that the above problem occurs mainly due to abnormality in the shape of the above singular memory cell or the coupling ratio, etc.
To be more specific, if a singular memory cell B (whose threshold value is singularly low) is present, the following problem arises: in the weak programming, a leak current flows into the singular memory cell B, as a result of which even when the actual threshold value of a normal memory cell A located on the same bit line as the singular memory cell B is equal to or higher than the voltage OEV level, it is mistakenly verified that the threshold value of the normal memory cell A is lower than the actual threshold value thereof. This is because the threshold of a memory cell is verified based on the amount of current in the memory cell. Therefore, the normal memory cell A whose threshold value is actually equal to or higher than the voltage OEV level is subjected to the weak programming. At this time, a drain voltage (drain stress) at the writing time is applied to the drain in the singular memory cell B, and thus a small number of electrons are injected thereinto, increasing the threshold value of the singular memory cell B. In such a manner, the weak programming is repeated until a leak current is prevented from flowing into the singular memory cell B being in the over-erased state. If the normal memory cell A is a memory cell the threshold value of which is close to the voltage EV level as shown in FIG. 3, when it is repeatedly subjected to the weak programming due to the presence of the singular memory cell B, its threshold value exceeds the voltage EV.
Accordingly, in the verifying processing, it is verified that the threshold value of the normal memory cell A exceeds the voltage EV level, and the processing to be performed is returned to the data erasing processing. However, after the singular memory cell B is re-subjected to the data erasing processing, its threshold is greatly lowered, since its characteristics does not vary (i.e., they depend on its shape), and its erasing speed is high. In this case, the weak programming is repeated a number of times in the same manner as stated above. In such a manner, the data erasing operation enters an infinite loop, and thus does not end.
Actually, when a nonvolatile semiconductor memory product is checked with respect to production specification, if the time for the erasing operation exceeds a given time period, the product is determined to be defective. Thus, according to the conventional method, the fraction of defective nonvolatile semiconductor memory productions is increased.
Furthermore, the above infinite loop also occurs in the case where the data erasing processing is performed on the memory cells in a block including a singular memory cell (which will be hereinafter referred to as a singular memory cell C) whose erasing speed is very low. In this case, the data erasing processing is performed such that the threshold value of the singular memory cell C is equal to or lower than the voltage EV levels as shown in FIG. 4, as a result of which the threshold values of most of the other memory cells in the block are equal to or lower than the OEV level. In such a manner, since the threshold values of memory cells located on the same bit line as the singular memory cell C are equal to or lower than the voltage OEV level, a leak current at the OFF time is large. Consequently, when each of the above memory cells is subjected to the verifying processing, it is mistakenly determined that the threshold of each memory cell is lower than the actual threshold value thereof, and thus the weak programming is performed more times than necessary. At this time, since the singular memory cell C is located on the same bit line as the above memory cells, the threshold value of the singular memory cell C is increased by a drain stress. Then, similarly, the other memory cells are subjected to the weak programming, as a result of which the threshold value of the singular memory cell C are further increased to exceed the voltage EV level as shown in FIG. 5. In such a state, finally, when the singular memory cell C is subjected to the verifying processing, it is verified that the threshold value of the singular memory cell C exceeds the voltage EV level, and the processing to be performed is re-returned to the data erasing processing. As a result, the thresholds of most of the memory cells other than the singular memory cell C become equal to or lower than the voltage OEV level again. Thus, a leak current increases, and the weak programming is repeated more times than necessary, in the same manner as in the above case. In such a manner, the erasing operation enters an infinite loop, and does not end, thus increasing the fraction defective.
As explained above, in the erasing processing in a nonvolatile semiconductor memory product, if an infinite loop occurs in which the erasing processing and weak programming are repeated, the nonvolatile semiconductor memory product is determined to be defective. Therefore, if the method of the conventional nonvolatile semiconductor memory device is adopted, the fraction of defective nonvolatile semiconductor memory products is increased. Furthermore, even if an infinite loop does not occur in a nonvolatile semiconductor memory product, when the weak programming is performed more times than necessary, the time required for the erasing operation is increased, thus degrading the function of the product, and increasing the time for testing the product.
Jpn. Pat. Appln. KOKAI Publication No. 8-255489 discloses the following technique: after the memory cell transistors are all subjected to a data erasing processing, it is determined whether a memory cell transistor or transistors being in an over-erased state are present or not with respect to each of a plurality of digit lines. If it is determined that a memory cell transistor being in the over-erased state is present, the memory cell transistor is specified, and weak programming (writing) is performed on the memory cell transistor only.